Incremental rate converter



NOV. 2, 1965 o, PLATTEN 3,216,00

INCREMENTAL RATE CONVERTER Filed May 27, 1959 2 Sheets-Sheet 1 lO/b- F lF /53 5| GATE g3 b a 25 \ELOAD GATE W4 52| INVENTOR. E G .2 oRRls H PLATTEN -BY/Mw AGENT Nov. 2, 1965 o. H. PLATTEN 3,216,000

INCREMENTAL RATE CONVERTER Filed May 27, 1959 2 Sheets-Sheet 2 FIG. 3

INPUT/u INVENTOR. ORRIS H. FLATTEN AGENT United States Patent O 3,216,000 INCREMENTAL RATE CONVERTER Orris H. Flatten, Fullerton, Calif., assigner to North American Aviation, Inc.

Filed May 27, 1959, Ser. No. 816,184 13 Claims. (Cl. 340-347) This invention relates to frequency responsive devices and more particularly to a device for producing a directcurrent analog signal indicative of the alegbraic sum of the rates of a pair of electrical pulse signals.

In many instances in computer systems there is obtained information which is in the nature of varying or incremental rate voltage signals at the output of .a digital computer. These signals may be in the form of constant amplitude pulse signals whose rate is directly proportional to the information being received from the computer. In order to utilize this information it is necessary to convert the incremental type of pulse signals to a direct-current -analog type signal which is proportional to the algebraic sum of the incremental rates of the input signals.

Devices of the prior art used to convert incremental rate signals received from a digital computer into a directcurrent signal utilized circuitry such as D.C. amplifiers having inherent drift errors limiting diodes and summing networks having inherent errors caused from leakage currents. Accordingly, the summed output of these converters did not meet the required accuracy.

Conversion of a pair of rate incremental pulse signals received from a digital computer to a D.C. current which is the algebraic sum of the pulse rates is achieved by the device of the present invention in ya highly accurate and relatively simple manner. High accuracy is obtained by utilizing transistors and low leakage silicon diodes taking advantage of the constant current properties of the transistors and inherent low leakage of the silicon diodes. A pair of transistorized switches are pro-vided which alternatively switch `a constant current source from one side to the other of an output load. The algebraic sum of the input signals is received by measuring the current through the load. The transistorized switches include unidirectional silicon diodes associated therewith to provide an accurate circuit with substantially no leakage current. Thus the average current flowing in the output load is a highly accurate measurement of the algebraic sum of the incremental rate of the input pulse signals.

It is therefore an object of this invention to provide an improved circuit for converting incremental signals to lanalog signals.

It is another object of this invention to provide a circuit for converting incremental rate pulse signals to analog signals.

It is still another object of this invention to provide a converter for computing the algebraic sum of the pulse rates of a pair of incremental pulse signals.

It is still another object of this invention to provide a transistorized incremental rate converter.

It is a further object of this invention to provide a position error converter for converting a pair of rate incremental pulse signals indicative of position error to an analog signal indicative of the algebraic sum of the rates of the incremental pulse signals.

Other objects of invention will become apparent from the following description taken in connection with the accompanying drawings, in which- FIG. l illustrates the invention in simplified block form; and

FIG. 2 further illustrates the principles of the invention in block form; and

FIG. 3 is a schematic diagram of the preferred embodiment of the converter of this invention.

3,2l6,000 Patented Nov. 2, 1965 Referring to FIG. 1, a simplified block diagram is shown illustrating the principles of the device of this invention. In FIG. 1 constant current generator 1 is connected through a pair of transistorized switches 2 and 3 across a load or measuring means 4. Switch 2 may, for example, lbe connected to be responsive to one pulse train input from a digital computer indicative of `a position error in one direction. Switch 3 may, for example, ,be connected to be responsive to a pulse train input from a digital computer indicative of a position error in the other direction. Switch 2, when receiving pulse inputs from a digital computer, for example, is connected to switch from the neutral position nl and n2 to positions a and b. When in the positions a and b constant current generator 1 is connected to supply current across load 4. With the polarities shown a positive current flows in a downward direction through load 4. When switch 3 is receiving a pulse train input from a digital computer the switch position is switched from neutral positions n3 and n4 to terminals c and d, thereby providing lcurrent flow from current generator 1 through load 4 in a direction opposite to the current flow when switch 2 is actuated. Load 4 may comprise, for example, suitaIble indicating means for measuring the average current flowing through load 4. Thus the average current flowing through 4 is the algebraic sum of the amount of pulse signals received by switch 2 and the amount of pulse signals received by switch 3. In this manner the resulting current iiowing through load 4 is indicative of the error from the digital computer, for example.

Referring to FIG. 2, there is further illustrated the principles of this invention in block form. Constant current generator 1 has one side (illustrated as the plus side) connected through gate 51 to one side 23 of load 4 to form a iirst electrical path. The plus side of current generator 1 is also connected through gate 52 to the other side 25 of load 4 to form a second electrical path. Gate 51 is controlled by the output of flip flop 53 and gate 52 is controlled by the output of flip flop 54. Flip flop 53 is connected to provide an electrical path defined by a D.C. source E having its plus side connected to the input of p iiop 53 and its minus side connected through ground to the minus side of current generator 1. The output of flip ilop 53 is connected to one side 23 of load 4. Flip ilop 54 also provides an electrical path defined by the plus side of source E, the input of ip flop 54 and side 25 of the load. Flip flop 53, responsive to signals from terminal 10 applied atits control input, operates to provide a path from one side of source E, through flip iiop 53, load 4, gate 52, current generator 1 and the other side of source E. Flip op 54, responsive to signals from terminal 20, operates to provide a path from one side of source E through flip flop 54, the load, gate 51, current generator 1, and the other side of source E. Thus it may readily be seen that responsive to input signals from terminal 10 a current path is provided through load 4 in the direction shown by arrow a and a current path in the reverse direction (arrow b) is provided responsive to signals from terminal 20.

Turning now to FIG. 3, there is shown a schematic diagram of a preferred embodiment of the circuit of this invention. In FIG. 3 constant current generator 1 of FIG. 1 is represented as transistor 5 which has its base connected to receive a constant source of D.C. potential represented by Eg. Transistor 5 is, for example, of the NPN type and has its emitter connected through a suitable resistor 6 to D.-C. source E1. E1 is selected to be more negative than E2, thus providing operating potentials on transistor 5 to maintain the transistor normally conducting. The collector of transistor 5 is connected to point 7. PNP transistors 8 and 9 form electronic switch 2 Vof FIG. 1, wim transistor 9 receiving incremental rate type 4pulse signals at `its `base from .input terminal 10 through resistor 11. Transistor 9 has its emitter connected to receive D.C. from source E7 and transistor 8 .has itsfemitter connected to receive D.C. from source E3. The emitter of transistor 8 is -connected through resistor i152 lto the base of transistor 9 and the collectoriof transistor 9,is coupled through resistor 48 to the basevof transistor 1 8. Transistors `8 and 9 operate as a monostable lswitch ,with transistor ,8 normally conducting and transistor 9 normally `cut olf. Upon receipt of 'a negative pulsesignal vfrom input terminal 10, transistor 9 conducts Yand :transistor 8 is cut off. The ceasing of input signals at terminal 10 causes transistor 8 toagain conduct and ,transistor 9 to cut olf. Similarly, transistors -14 and 15 of the PNP 'itypecomprise electronic switch 3 of FIG. l. Transistor j-14 has its emitter connected to receive D.-C. :from source Esand transistor 15 Ihas its emitter connected to receive D.C. l.from source E7. Transistors 14 and 15 are cross-.coupled'to form a monostable switch with the .base of transistor 14 connected through resistor 16 to Vthe collectorof transistor 15 and the base of transistor 15 connected through resistor 17 to theemitter of transistor l14. Transistor A1.4 is normally conducting and transistor 115 is normally cut olf. A negative pulse signal received from input .terminal 20 through resistor 19 causes transistor 1'5 to conduct and cuts 01T transistor 14. The ceasing of input signals at terminal 2t) returns transistor 14 to its normal vconducting state and cuts olf transistor 15. Transistor I9 is connected through diode 22 to terminal 23 of load 4. lDiode 22, preferably of the silicon junc- -tion type, allows current to flow from E7 through transistor 9 (when conducting as a result of input signals from terminal 10) to terminal 23 of load 4. When transistor A9 is cut oli diode 22 prevents any leakage of current tendling to flow in the reverse direction. Diode 24 is connected to the collector of transistor 8 and is poled in a direction to prevent 4the ow of current from E3 through transistor .f8 fto load 4 when transistor 8 is turned on. Diode 24 also provides a Alow impedance current path through resistor28 to E1 to prevent any current from ilowingfthrough kdiode I42 when transistor I9 is conducting. 'Diode 26 connects the collector of transistor 15 to terminal 25 of load 4, with current owing from E7 through the emitter-collector of -transistor 15 (when conducting as a result of aninput signal `from terminal 20) through diode 26to terminal 25. Diode 26, as diode 22, is preferablyfof Vthe silicon `junction type to prevent any leakage current -flowing when linput -signals are not being received tromterminal 20. Diode 27 risconnected to the-collector of transistor 14 and ispoled in a direction-to prevent current flow from transistor 14 to load 4 when transistor '-14 `is conducting and also to provide a low impedance path awayfrom diode 39 vrwhen transistor 15 is conducting. Resistors '28.and 29 respectively connect the cathode plates of diodes 24 and l27 to receive D.C. from source El to provide a negative bias-potential preventing undesirable current from llowing through load 4. Similarly, resistors 30and 31 connect the anode plates of diodes 22 and 26 respectively to D.C. source E1. Operating potentials on thebase of transistors 8 and `14 are received from a D.C. source E4 connected through resistor 34 to the base of transistor 8 and through resistor 35 to the base of transistor 14. Source E4 is of a more Apositive potential than source E3, and provides a bias potential on the base of transistor 8 to maintain transistors 8 and 14 turned off when there is an input signal. Constant current :generator .Sis connected Vto provide a current path through .load k4 `when transistor9 is turned on upon receipt :of la lpulse signal from input terminal 10. Terminal25 ofload 4,is.connected through resistor 38 and .diode 39 to Vpoint 7. Diode 39 `is poledin a direction to allow theA ow of current from terminal ,25 through the collectoremitter of transistor .5.. Similarly, ytransistor `is connected `to provide acurrent path Athrough load 4 when p Yin switch 2.

transistor 15 is turned on upon receipt of a signal from input terminal 20 with terminal 23 of load 4 being connected through resistor 41 and diode 42 to point 7. Diode 42 is poled in a direction to allow the flow of current from terminal 23 through the collector-emitter circuit of transistor 5. Capacitor 45 is connected across terminals 23 and 25 of load 4 to provide a smoothing operation for the current signals received thereby.

In the circuit of FIG. 3 a quiescent condition exists when no input signals are received from terminals 10 and 20. Transistor 8 is conducting and transistors 9 is cut or' In switch 3 transistor 14 is conducting and transistor -1-5 is cut off. With transistor 9 cut oft, there is no current path provided between `source E7 and terminal 23 of load 4. Similarly, diode 24 prevents a current path from being created between source E3 and terminal 23 of load 4. Transistor ,15 is cut off thereby preventing the ilow of current from source E1 to terminal 25. Diode 27 prevents the flow of current from source E3 to terminal 5. Thus there is no current path between a rsource and the collector of transistor 5. Transistor 5 is in a condition to be conducting since source E1 is more negative than source E2, but because of the fact that point 7 is not connected to receive a current flow from D.C. sources 3 or '7, the collector of transistor 5 is floating at some quiescent potential and the base emitter circuit of transistor 5 is acting as a diode.

Input pulse signals received from terminal 10 cause transistor 9 to conduct and transistor 8 to cut off. A current path is created comprising the circuit of D.C. source E7, the emitter-collector path of transistor 9, diode 22, terminal 23 of load 4, terminal A25, resistor 38, diode 39, point 7, the collector-emitter path of conducting transistor 5, resistor 6, and source E1. E7 might be, for example, the B-lsupply of a D.C. source, and El may be the B- supply of a D.C. source, thus completing the current path. Load 4 has current flowing from terminal 23 to 25 for a predetermined time, determined by the operating conditions established at current generator 5. The pulse signals received from input terminal 10 may `be of `a constant amplitude, thus establishing an accurate measurement of current ow through load 4. During the time when input signals are received from terminal 10, no input signals are received from terminal 20, transistor 14 is conducting, transistor 15 is cut oi, with the switch 3 being inactive in the operational function. Typical values of potential may be, for example: E128 V.; liz- 14 v.; ET-ground; E3+ 14 v.; and E4-+28 v.

Now, assuming an input signal from terminal 20, transistor 15 is turned on and transistor 14 is cut oit. A current path between transistor 5 and load 4 is created comprising D.C. source E7, the e-mitter-collector path of transistor 15, diode 26, terminal 25 to terminal 23 of load 4, resistor 41, diode 42, point 7, the collector-emitter path of transistor 5, resistor 6, and source E1. Thus it may -be seen that the current flow now established through load 5 is in an opposite direction to the flow of current when input signal-s were received from terminal k10. The time during which current is ilowing through load 4 is directly proportional to the Ifrequency of the pulse signals received at input terminal 20. Thus the flow of current through load 4 in the direction of terminal 25 to 23 is a measurement of the incremental rate of the input pulse signals at terminal 20. Capacitor 45 serves to charge and discharge pulse signals, ,thereby smoothing the .circuit operation. The current owing through load 4 is thus an algebraic sum of the number of incremental rate of pulse signals at terminal 10 andthe rate of pulse signals at terminal '20. A D.C. analog current signal is received through load 4 which is directly proportional to the difference between the incremental rate of signals at terminal 10 and the incremental rate of signals at terminal 20. Load 4 may comprise any suitable measuring means Ifor measuring direct-current flow.

During the operation of the converter of FIG. 3 when input signals are received from terminal or terminal 20, diodes 22, 24, 26, 27, 39 and 42 all operate to prevent lany other current from flowing through load 4 other than the current described in the current path between E, and E1, current flowing throu-gh transistor 9 when input signals are received from terminal 10, and current flowing through transistor when input signals are received 'from terminal 20. For example, when input signals are received from terminal 10 and a current path is created lbetween source E7, transistor 9, diode 22, load 4, resistor 38, diode 39, and point 7, leakage current is prevented from flowing through diode 27 by reason of the positive back .bias signal on the cathode of diode 27 presented by the conducting transistor 14. Diode 26 of course prevents any flow of current from terminal 25 to the collector of transistor 15. When input pulse signals cease from terminal 10, transistor 9 is cut ofi and transistor 8 conducts. Diode 22 now prevents any flow of current from terminal 23 to transistor 9, and diode 24 prevents any ilow of current through conducting transistor 8 to terminal 23 of load 4. Diodes 39 and 42 prevent any fiow of current other than through the collector of transistor 5 when received -from terminals 23 and 25 of load 4. Thus it may be seen that the association of the silicon diodes described with the transistors of electronics switches 2 and 3 provides a circuit which is highly accurate measurement of the incremental rate between the pair of input signals being received through load 4.

Load 4 may comprise any type of measuring system such as, for example, a recorder for measuring the average D.C. current flowing therein. D.c. sources El, E2, E3, E4, and E, are shown for illustration purposes only and may be of different polarities provided the associated transistor circuitry is compatible therewith. For example, electronic switch 2 may have transistors of the NPN type and transistor 5 may be of the PNP type with the resulting D.C. operating potentials adjusted accordingly by means well known in the art to provide operating potentials. It is essential that the diodes associated with the transistors -be connected .as shown in order to prevent undesirable leakage current from flowing through load 4.

The circuit shown in FIG. 2 is particularly adapted to a system wherein output signals are received from a digital computer which are indicative of a position error of an airplane. For example, in FIG. 2 input terminal 10 is responsive to the output of a digital computer for position error signals in one direction and input terminal is responsive to the output of a digital computer for position error signals in the other direction.

Although the invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of this invention being limited only by the terms of the appended claims.

I claim:

1. Frequency determining means comprising a constant current generator, switch means connected to be responsive to first and second pulse trains respectively indicative of an incremental rate, measuring means, gate means responsive to said switch means for alternatively connecting said current generator to said measuring means to cause current flow through said measuring means in one direction or the direction opposite said one direction and to cause the output of said measuring means to be an indication of the algebraic sum of the frequency of said first and second pulse rates.

2. Frequency determining means comprising means for generating constant current, first and second input terminals connected to receive first and second4 pulse trains respectively, load means, first electronic switch means connected to said first input terminal for connecting said constant current generating means across said load means to cause current fiow through said load in one direction,

and second electronic switch means connected to said second input terminal for connecting said constant current generating means across said load means to cause current flow through said load in a direction opposite said one direction.

3. Frequency determining means comprising means for generating constant current, load means, first switch means for connecting said constant current generating means across said load means to cause current to flow through said load means in a first direction, second switch means for connecting said constant current means across said load means to cause current to flow through said load means in a second direction, said first and second switch means being operatively responsive to a pair of pulse trains.

4. Frequency determining means comprising constant direct current generating means having first and second output terminals, current measuring means having rst and second input terminals, first switch means operatively responsive to a first pulse train for coupling said generating means first terminal to said first input terminal and said generating means second terminal to said second input terminal to provide current flow through said measuring means in one direction, second switch means operatively responsive to a second pulse train for coupling said generating means first terminal'to said second input terminal and said generating means second terminal to said first input terminal to provide current flow through said measuring means in a direction opposite said one direction.

5. The combination recited in claim 4 wherein said first and second switch means each comprise a pair of transistors operatively coupled to form a monostable switch coupled to assume its unstable state in the presence of said pulse trains, one of said transistors being connected to couple said constant current generating means to said measuring means when said switch is in its unstable state.

6. In combination, means for generating a constant current, means for measuring current, a pair of input terminals, each of said terminals being connected to receive a separate pulse train, first means connected to one of said input terminals for providing a first current path between said constant current generating means and said current measuring means in response to one of said pulse trains, to drive current through said measuring means in a first direction, second means connected to the other of said input terminals for providing a second current path between said constant current generating means and said current measuring means in response to a second of said pulse trains to drive current through said measuring means in a second direction.

7. The combination recited in claim 6 wherein is included means for preventing fiow in said first current path when current is flowing in said second current path.

8. The device as recited in claim 7 wherein said means for preventing ow in said rst current path when current is flowing in said second current path comprises a plurality of diodes connected in said current paths.

9. In combination, a constant current generator, a load, first and second gates, a first electrical path from one side of said generator to one side of one of said gates, a second electrical path from said one side of said generator to one side of the other of said gates, each of the other sides of said gates being connected to an opposite side of said load, and first and second switch means for controlling said first and second gates respectively, said first and second switch means each providing a separate electrical path between a separate side of said load and the other side of said current generator.

10. An incremental rate converter for converting a first and second trainr of pulses indicative of positive and negative signals respectively to a D.C. signal indicative of the algebraic sum of said pulse signals comprising a constant current generator, a load, first switch means Aresponsive .to said irst train of pulses for connecting said current generator acr-oss said load to cause current ilow .through said load in `one direction, `and second switch means ,for connecting rsaid current generator across said loadto cause current ow through said load in a direction .opposite said one direction, to cause a D.C. signal in accordance `with the algebraic sum of the `rates of said positive and lnegative pulse signals `to be produced across said load.

11. In combination: a-constant current source; an electrical load; ,a rst monostable ,multivibrator adapted t0 channel the current from said current source through said load `in a first direction when said first multivibrator is in its unstable state; a second monostable multivibrator adapted to channel the current from said current source in a second direction Vthrough said `load when said second multivibrator is .in yan unstable state; each of said multivibrators having input terminals connected to ca use `said multivibrators to assume an ,unstable ,state when ya signal is applied thereto.

12. ,In combination: a ,transistor current source; an electrical load; two current paths, each connected to cause current to flow vfrom such transistor through said load in different directions; at least one diode in each of said current paths, said diodes being back biased to prevent conduction; a pair of current lreturn paths connected to said load, including diode means connected in series therewith vand normally back biased; and mono- 8 stable multivibrator means `connected to said current paths to cause currents selectively to be .passed in one direction or the other through saidload.

13. In combination: a irst NfP-N transistor; a irst and second diode, each connected by their cathode to the collector of said transistor; an electrical load, Lconductively connected at opposite terminals to the anodes of said diodes; `first and second monostable multivibrators, connected to back-,bias said diodes, respectively, .when said multivibrators are Vin their-stablestate andto ,remove said bias when said multivibrators are .in their unstable state; and means vconnected to saidmultivibrators to cause them to assume their unstable state .in response to ,an Ainput signal.

OTHER REFERENCES Page 782, 1955 edition, Electronic and Radio Engineering, by Terman. Y

MALCOLM A. MORRISON, Primary Examiner.

WALTER W. BURNS, JR., ABRAHAM BERLIN,

Examiners'. 

1. FREQUENCY DETERMINING MEANS COMPRISING A CONSTANT CURRENT GENERATOR, SWITCH MEANS CONNECTED TO BE RESPONSIVE TO FIRST AND SECOND PULSE TRAINS RESPECTIVELY INDICATIVE OF AN INCREMENTAL RATE, MEASURING MEANS, GATE MEANS RESPONSIVE TO SAID SWITCH MEANS FOR ALTERNATIVELY CONNECTING SAID CURRENT GENERATOR TO SAID MEASURING MEANS TO CAUSE CURRENT THROUGH SAID MEASURING MEANS IN ONE DIRECTION OR THE DIRECTION OPPOSITE SAIDE ONE DIRECTION AND TO CAUSE THE OUTPUT OF SAID MEASURING MEANS TO BE AN INDICATION OF THE ALGEBRAIC SUM OF THE FREQUENCY OF SAID FIRST AND SECOND PULSE RATES. 